1. Field of the Invention
The invention generally relates to transistor devices which have a dynamic threshold and more particularly to a dynamic threshold device which has increased current capabilities.
2. Description of the Related Art
Silicon-On-Insulator (SOI) technology, which is becoming of increasing importance in the field of integrated circuits, deals with the formation of transistors in a relatively thin layer of semiconductor material overlying a layer of insulating material. Devices formed on SOI offer many advantages over their bulk counterparts, including: higher performance, absence of latch-up, higher packing density, low voltage applications, etc. However, SOI circuits, like other electronic circuits, are: First, susceptible to electrostatic discharge (ESD), a surge in voltage (negative or positive) that occurs when a large amount of current is applied to the circuit; and second, in need of providing an ideality (a constant voltage swing of 60 mV/decade over several decades of current) for analog applications, such as in phase-locked-loop circuits, voltage regulators, and band gap reference circuits.
To discharge ESD impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diode circuits, do not work well on SOI because of the presence of the SOI buried oxide. That is, conventional diodes on SOI have small current drivability because the current is carried laterally and is limited by the thickness of the semiconductor material. Thus, developing a new approach or a new type of diode was necessary for adequate ESD protection for SOI circuits.
ESD robustness is also important for SOI driver (buffer) and receiver circuits. Receiver circuits, pass transistors, test transistors, feedback keeper elements and other auxiliary transistors on input pins must be overvoltage tolerant to protect from ESD events, electrical overstress, and other high current and voltage conditions. Hence, robust elements are needed to provide ESD robust SOI receive circuits.
For I/O networks, off-chip drivers must also provide ESD robust pull-up and pull down elements. Hence, n-channel or p-channel SOS transistors, used as both pull-up or pull-down elements must provide over shoot and undershoot protection, electrical overstress protection and ESD protection.
The invention provides a dynamic threshold device which is useful for more than just diodic functions. For example, as explained in greater detail below, the invention can act as a lower trigger device with extremely high current loads to provide excellent ESD protection.
In one aspect, the invention provides a structure, method and apparatus which uses a body-charging element in receiver and I/O driver circuits, peripheral circuits, and core circuitry in an SOI chip. The invention uses an SOI body-limiting element in receiver and I/O driver circuits, peripheral circuits, and core circuitry to provide a more robust network from overvoltage and electrical overstress in an SOI chip.
In addition, the invention provides a structure, method and apparatus which uses an SOI body-augmenting network which modulates the SOI body potential and provides an alternative current path in a SOI receive and driver network for peripheral circuits and core circuitry to provide a more robust network. The invention also uses a SOI polysilicon-gated lateral undirectional unipolar bipolar transistor (Lubistor) as a body-charging element network for an SOI MOSFET. The invention also uses an SOI body- and gate-coupled SOS MOSFET as a body charging element network.
In addition, the invention provides a structure, method and apparatus which uses an SOI Lubistor elements for a body-reference network. The invention includes an SOI body- and gate-coupled MOSFET network for a body-modulation network and provides electrostatic discharge protection of SOI circuitry. The invention also provides a means for electrical overstress (EOS), electrostatic discharge (ESD), undershoot and overshoot protection to receiver, I/O driver and peripheral or core-circuitry for SOI circuitry. The invention uses a reference control network for SOI body potential modulation for receiver and I/O driver peripheral or core circuitry, for improved electrostatic discharge robustness of receiver and I/O drive peripheral circuitry and core circuitry.
Thus, the invention provides a structure and method for a body coupled driver circuit which includes a pull-up stage having a first transistor, and a pull-down stage having a second transistor (the first transistor and the second transistor have bodies coupled to one of a reference voltage and a pad node). The bodies of the first transistor and the second transistor are connected to one of the reference voltage and the pad node via a network. The network includes resistors in series, resistive transistors, lateral diodes, dynamic threshold transistors, a body charging element, and a body limiting transistor.
Another embodiment of the invention is a silicon-on-insulator (SOI) metal oxide silicon field effect transistor (MOSFET) device which includes a source, drain, body, and circuit control network connected between the drain and the source (the circuit control network controls a potential voltage of the body and provides overvoltage protection to the SOI MOSFET device). The circuit control network provides a parallel current path to the SOI MOSFET device, establishes the parallel current path, and charges the body of the SOI MOSFET device. The circuit control network includes a body-limiting element. The circuit control network includes at least one resistor element between the drain and the body, a second resistor element connected between the source and the body, at least one SOI lateral polysilicon gated undirectional bipolar transistor (Lubistor) device between the drain and the body, a second SOI lateral polysilicon undirectional bipolar transistor (Lubistor) connected between the body and the source, at least one SOI body-, gate-, and drain-coupled dynamic threshold MOSFET in a diode configuration between the drain and the body, and a second SOI body-, drain-, and gate-coupled SOI dynamic threshold MOSFET in diode configuration connected between the body and the source.
The device further includes at least one secondary SOI MOSFET between the drain and the body and a third SOI MOSFET connected between the body and the source. The device further includes an input pad connected to the drain, an inverter input connected to the source, the device forming a half-pass transistor for a receiver network, and an input pad connected to the drain and a substrate connected to the drain, the device forming a pull-down element. The device can be gunning transistor logic (GTL) I/O driver. The device can further include an input pad connected to the source, a Vdd power supply connected to the drain, an n-channel SOI device connected between the input pad and the Vdd power supply, an input pad connected to the body, a second SOI MOSFET connected to the source, and a power supply voltage connected to the source. The device can form a pull-down network. The SOI MOSFET and second SOI MOSFET include p-channel transistors and the device further includes a chip substrate. The device can form a mixed voltage CMOS I/O driver. The device further includes an n-channel pull-down transistor, Vdd power supply connected to the n-channel pull-down transistor, first p-channel pull-up transistor forming a second control network, and a chip substrate connected to the p-channel pull-up transistor. The circuit control network controls a body potential of the first n-channel pull-down transistor. The p-channel pull-up transistor is connected to Vss. The circuit control network charges the body and limits the voltage of the body to a set reference voltage and charges the body. The device further includes a plurality of resistors, second SOI MOSFETs, SOI Lubistors, and SOI body-and-gate-coupled SOI diodes in one of a parallel and a series configuration connected to the drain and the source to modulate a potential of the body and provide a second current path parallel to the SOI MOSFET device. The device further includes a capacitor and control elements connected to one of the body and the gate for triggering the SOI MOSFET.